1. Technical Field
The present invention is directed to a method, system and apparatus for instruction tracing with out of order speculative processors.
2. Description of Related Art
Instruction traces are used by software and hardware developers to capture the exact flow of instructions and addresses executed on a computer system. For maximum value, the instruction traces must contain all addresses for both instructions and data, address translation information to map the effective addresses to virtual and real addresses, the actual instruction image processed, and flow information to indicate the order instructions and data were processed. The resulting trace must be in the original order as coded by the programmer. Regardless of the order in which data is collected, the processor should run as close to full speed as possible while being traced. If the execution of instructions slows down considerably while the rest of the system (memory, input/output devices, other processors) continue to run at full speed, the resulting trace will not accurately portray the instruction stream at full speed. Input/output will seem to return much faster with fewer instructions between input/output request and return. Lock contention due to other processors will be distorted since the processor, under trace, cannot retry locks as quickly as the other processors.
Modern processors use out of order execution and speculative execution to increase performance. As a result, it is difficult to capture instruction and address flow in program order. Additionally, speculation results in the execution of instructions that may not be part of the actual program flow. To further complicate tracing, many modern processors transform the original instruction coded by the programmer into one or more internal instructions. Once the original instruction is transformed, it is lost.
Existing instruction trace methods, both hardware and software, disable the out of order nature of the processor by interrupting the processor after every instruction has completed. This mechanism has the undesirable effect of slowing down the processor and changing the execution behavior (by eliminating out of order execution and possibly reducing speculation). Slowing down the processor under trace distorts the instruction stream, possibly to the point where it is not representative of the actual execution stream.
Therefore, it would be advantageous to have a method and apparatus capable of performing instruction traces with out-of-order processors and speculative processors in which the nature of the operation of these processors is not altered during the trace.
The present invention is directed to a method, system and apparatus for instruction tracing with out of order speculative processors. With the present invention, information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device for use in reconstructing an instruction stream of an out-of-order speculative processor. In addition, information corresponding to instructions fetched by the processor is stored in the trace storage device in sequential order as they are fetched.
When a cache load is necessary to obtain instructions that are not already stored in the instruction cache or data that is not already stored in the data cache, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during fetching of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions fetched is known from the fetched instructions information stored in the trace storage device.
Thus, with the present invention the instruction stream of fetched instructions may be obtained from the information stored in the trace storage device. Thereby the instruction stream may be reconstructed for debugging purposes. Other features and advantages of the present invention will be described in, or will become apparent to those of ordinary skill in the art in view of, the following description of the preferred embodiments.